Tutorial for the Design of FIR Digital Filters over FPGA
| dc.contributor.author | Hernández Suárez, César Augusto | spa |
| dc.contributor.author | Gomez, Edwar Jacinto | spa |
| dc.contributor.author | Salcedo Parra, Octavio José | spa |
| dc.date | 2008-11-30 | |
| dc.date.accessioned | 2019-09-19T21:37:54Z | |
| dc.date.available | 2019-09-19T21:37:54Z | |
| dc.description | This article presents a different and simple methodology in the design and implementation of digital filters with finite impulsional response, over a reconfigurable architecture like FPGA XC3S200. In this development were used CAD tools as FIR toolbox and ISE of Xilinx, obtaining with that results in record time, optimization in the hardware resources used and good performance in frequency, desirable characteristics in the development of systems oriented to the digital signal processing. | en-US |
| dc.description | Este artículo presenta una metodología diferente y sencilla en el diseño e implementación de filtros digitales con respuesta impulsional finita, sobre una arquitectura reconfigurable como la FPGA XC3S200. En este desarrollo se emplearon herramientas CAD como "FIR toolbox" e "ISE" de Xilinx, obteniendo con ello resultados en tiempo record, optimización en cuanto a los recursos de hardware utilizados y un buen desempeño en frecuencia, características deseables en el desarrollo de sistemas orientados al procesamiento digital de señales. | es-ES |
| dc.format | application/pdf | |
| dc.format | text/html | |
| dc.identifier | https://revistas.udistrital.edu.co/index.php/reving/article/view/2115 | |
| dc.identifier | 10.14483/23448393.2115 | |
| dc.identifier.uri | http://hdl.handle.net/11349/19492 | |
| dc.language | spa | |
| dc.publisher | Universidad Distrital Francisco José de Caldas | en-US |
| dc.relation | https://revistas.udistrital.edu.co/index.php/reving/article/view/2115/2800 | |
| dc.relation | https://revistas.udistrital.edu.co/index.php/reving/article/view/2115/2801 | |
| dc.source | Ingeniería; Vol 14 No 1 (2009): January - June; 13-17 | en-US |
| dc.source | Ingeniería; Vol. 14 Núm. 1 (2009): Enero - Junio; 13-17 | es-ES |
| dc.source | 2344-8393 | |
| dc.source | 0121-750X | |
| dc.subject | Filters | en-US |
| dc.subject | FIR | en-US |
| dc.subject | FPGA | en-US |
| dc.subject | VHDL. | en-US |
| dc.subject | Filters | es-ES |
| dc.subject | FIR | es-ES |
| dc.subject | FPGA | es-ES |
| dc.subject | VHDL. | es-ES |
| dc.subject | Filters | es-ES |
| dc.subject | FIR | es-ES |
| dc.subject | FPGA | es-ES |
| dc.subject | VHDL. | es-ES |
| dc.title | Tutorial for the Design of FIR Digital Filters over FPGA | en-US |
| dc.title | Tutorial Para El Diseño De Filtros Digitales Fir Sobre Fpga | es-ES |
| dc.type | info:eu-repo/semantics/article | |
| dc.type | info:eu-repo/semantics/publishedVersion | |
| dc.type.coar | http://purl.org/coar/resource_type/c_6501 |