Herramienta de software para el desarrollo de descripciones de hardware utilizando VHDL a partir de modelos gráficos
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Universidad Distrital Francisco José de Caldas
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Con el objetivo de agilizar y facilitar el proceso de diseño de hardware se han realizado investigaciones relacionadas con la generación automática de descripciones VHDL a partir de modelos gráficos. En este documento se describe una herramienta de software que permite obtener la descripción VHDL a partir de un diagrama ASM o de un diagrama de componentes. Esta herramienta tiene la característica de que pueden reutilizarse descripciones ya creadas como nuevos componentes y la información contenida en diagramas ASM como parte de nuevos diagramas ASM. La herramienta es utilizada para generar la descripción VHDL de 15 circuitos comunes a partir de sus diagramas de componentes y ASMs, obteniéndose en un 53% de los casos descripciones equivalentes y en el resto de casos aproximadas.
With the purpose of making the process of hardware designquicker and easier, a number of investigations have been conducted concerning the automatic generation of VHDL descriptions based on graphic models. In this document, a software tool that generates VHDL descriptions based on either ASM diagrams or components diagrams will be presented. The characteristics of this tool allow aVHDL description already created to be reused like a newcomponent. Additionally, the information contained in an ASM diagram can be reused as part of new ASM diagrams. The tool is used to generate the VHDL description of 15 well-known circuits from both their component diagrams and their ASM diagrams, obtaining an equivalent description in 53% of the cases and approximate descriptions in the remaining cases.
With the purpose of making the process of hardware designquicker and easier, a number of investigations have been conducted concerning the automatic generation of VHDL descriptions based on graphic models. In this document, a software tool that generates VHDL descriptions based on either ASM diagrams or components diagrams will be presented. The characteristics of this tool allow aVHDL description already created to be reused like a newcomponent. Additionally, the information contained in an ASM diagram can be reused as part of new ASM diagrams. The tool is used to generate the VHDL description of 15 well-known circuits from both their component diagrams and their ASM diagrams, obtaining an equivalent description in 53% of the cases and approximate descriptions in the remaining cases.
Palabras clave
VHDL, ASM, components, tool, XML, hierarchy., VHDL, ASM, componentes, herramienta, XML, jerarquía.