Please use this identifier to cite or link to this item: http://hdl.handle.net/11349/21022
Title: 8-bit softcore microprocessor with dual accumulator designed to be used in FPGA
Author: Martinez Santa, Fernando
Sáenz Rodríguez, William
Rivera Sánchez, Fernando
Keywords: embedded microprocessor
harvard architecture
RISC
softcore
FPGA
Verilog
dual accumulator
Publisher: Universidad Distrital Francisco José de Caldas. Colombia
Description: Context: This paper is presents the design and implementation of an 8-bit softcore RISC microprocessor able to be run on space-optimized FPGA, in order to be used for embedded applications.Method: The design of this microprocessor was developed in Verilog hardware description language and can be implemented in FPGA from different manufacturers; therefore, the user has only to define the input and output ports according to the type of FPGA. This is an accumulator-type processor, but it has two different accumulators that can be used as pointers for indirect addressing. The processor is Harvard with a RAM of 8x256 bits, and a ROM that can be resized from 17x252 bits to 17x8K bits. Additionally, it has one 8-bit input port, one 8-bit output port, and one 8-bit address port, which means that the processor can address more than 256 8-bit output ports/devices. The same applies for input ports.Results: The developed processor, named “ZA-SUA,” was compared with PICOBLAZE softcore and other three similar processors of free distribution in the Web, and some improvements over those were found. Criteria such as the Flip Flops used, occupied LUTs, Slices in use, and maximum delay of each processor were analyzed, all these results were obtained from the implementation of the processors in the Xilinx FPGAs.Conclusions: The designed architecture is composed by two accumulators, which can be used either as source or destination for the operation of the ALU. This fact gives some flexibility to the design, doing it better than a single-accumulator processor, and getting it closer to the register-based processors.
URI: http://hdl.handle.net/11349/21022
Other Identifiers: https://revistas.udistrital.edu.co/index.php/Tecnura/article/view/12976
10.14483/22487638.12976
Appears in Collections:Tecnura

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